The present invention is directed to a method of forming a dual inlaid interconnect structure in semiconductor devices, including microprocessors, DSPs, microcontrollers, FSRAMS, etc. Dual inlaid interconnect techniques are generally known in the art, and have been found to be advantageous by permitting simultaneous formation of interconnected, metal-filled trenches and vias. However, numerous problems exist with current dual inlaid technology, particularly with respect to use of such technology with so-called low-k dielectrics, materials having a dielectric constant below 3.5, more preferably, below 3.0. In connection with prior art techniques of forming dual inlaid structures, reference is made to FIG. 9.
FIG. 9 depicts a stage in the method of forming a dual inlaid structure at a step where via opening 400a is formed in trench interlevel dielectric (ILD) layer 320. More particularly, FIG. 9 depicts a structure having substrate 100, formed of a low-k material or a conventional oxide material, in which metallic interconnects 120 are formed. As known in the art, metallic interconnects can be formed of copper, aluminum, gold, silver, etc. Metal interconnects 120 are provided for lower level electrical connection to active devices formed along the active region of the semiconductor substrate (not shown). An etch stop layer 160 is deposited over substrate 100, including metal interconnects 120. Etch stop layer 160 is generally formed of a nitride material, such as silicon nitride, silicon oxynitride, or a composite thereof. Conventionally, the etch stop layer is formed by a plasma enhanced chemical vapor deposition process. Then, a via ILD layer 200 is deposited on the etch stop layer 160. Via ILD layer 200 is generally formed of an oxide, such as silicon dioxide formed by PECVD. Further, etch stop layer 220 is formed on via level dielectric 200, in a similar fashion to etch stop layer 160 formed on substrate 100. Trench level dielectric 320 is then formed on etch stop layer 220, in a similar fashion to the via ILD layer 200.
After completing the dual dielectric layer structure including dielectric layers 200 and 320, etching is executed to form a lower via 400 and a trench 500, both of which are subsequently filled with a conductive metal. Particularly, a hard mask 340 is formed on trench level dielectric 320. The hard mask 340 is be formed in a similar fashion to the etch stop layers 160 and 220. A photoresist 360 is then formed on hard mask 340. The materials of photoresist 360 are particularly chosen depending upon the particular wavelength utilized for exposure, such as I-line or DUV (deep ultra-violet) processing. Such photoresist materials are generally spun-on and are readily commercially available.
FIG. 9 particularly shows a first step for forming what is known in the art as the conventional via first-trench last (VFTL) process, wherein via 400 is formed in the via ILD layer 200 prior to trench 500 within trench ILD layer 320. Here, after exposure and developing of photoresist 360, hard mask 340 is etched, followed by subsequent etching of via opening 400a in the trench ILD layer 320. Thereafter, additional etching steps are carried out to form via 400 and trench 500. Via 400 and trench 500 are formed by any one of several conventional techniques. For example, etch stop layer 220 is etched, followed by partial etching, such as to level 400b, to leave a dielectric material over etch stop layer 160. At this point, photoresist 360 is removed by the etching process, and a new photoresist layer (not shown) is formed to define trench 500. During etching to define trench 500, the remaining portion of dielectric material below level 400b is simultaneously removed.
A final etching step is be executed to remove a portion of etch stop layer 160 superposed on metal interconnect 120, followed by metal fill to fill via 400 and trench 500 and provide electrical connection to metal interconnect 120. While not shown in the plane of FIG. 9, trench 500, after metal fill, forms a line that extends into and out of the plane to provide electrical contact to the other in trenches and vias. The vias, on the other hand, only provide electrical connection vertically through the structure, to the contacts 120. Accordingly, the vias generally extend perpendicularly with respect to the plane of FIG. 9 only a short distance. For example, via 400 may be round or square, the width of the via 400 shown in FIG. 9 defining the diameter or side respectively.
The process as described above in connection with FIG. 9 is known in the art, particularly with respect to via and trench ILD layers formed of an oxide dielectric material. However, the present inventors have recognized several problems with this process when applied to low-k dielectrics for the via and trench ILD layers. Particularly, it has been observed that the materials used for forming the photoresist 360, as well as the developer for such materials, interact with the exposed outer walls within via opening 400a, along zone 320a. In particular, it has been observed that the low-k dielectric material tends to swell due to absorption of solvent used in connection with the photoresist and/or the developer used for forming trench 500. Additionally, unwanted chemical reactions take place between the low-k dielectric material along zone 320a and the photoresist, the solvent used with the photoresist, and/or the developer used for developing the photoresist. As is evident, the swelling of the low-k dielectric material along via opening 400a can be deleterious, causing problems with control of critical dimensions (CD) and ILD stack integrity, resulting in cracking of the hardmask 340, for example. Further, the unwanted chemical reactions may adversely affect the photo-active properties of the photoresist layer for forming trench 500, or the dielectric properties along zone 320a.
Further, multilevel metal (MLM) interconnects may also be made by other techniques, such as utilizing a single inlaid process. In this known process, a single inlaid of metal trace is deposited in the via ILD layer, prior to formation of the trench ILD layer thereon. Accordingly, the metal deposited in the via requires CMP (chemical mechanical polishing) prior to formation of subsequent layers thereon, including appropriate etch stop layers and the trench ILD layer. Not only does this process require multiple steps of depositing metal to fill the vias and trenches, but also multiple CMP steps, which are difficult to regulate and clean-up after.
In view of the foregoing problems with application of the dual inlaid process to low-k dielectric materials, and the disadvantages with single inlaid process, the present invention has been developed.